# An Introduction to Finite State Machine Design

module sw_3way(
input A,
input B,
input Clk,
output Y
);
reg q,Qp;
always @ (A,B,q)
begin
// next states
Qp = (~A&~q)|(~B&~q)|(A&B&q);
end
always @ (posedge Clk)
begin
q <= Qp;
end
assign Y = q;
endmodule

Now comes the moment of truth (or call it the moment of fault if you will). The code is programmed to our CPLD board, with signals A,B,Y,Clk assigned to pins 39,40,38,5, respectively, of XC9572. This video captures the test result

Obviously, the circuit fails to meet the desired functionality ( time to say “I knew it!”.) As the audience might already figure out, the system clock is normally much faster than an input signal from human operator. When a switch is pressed (AB = 01 or AB = 10), we can see from the state diagram in Figure 1 that the state transition between S0 and S1 could happen many times, depending on the clock frequency. The final state after that switch is released is therefore unpredictable.

A quick fix to make this circuit works, sort of, is to use a very low clock frequency to assure that only one transition happens between each button push. Of course, this clock much match the user’s timing of pressing/releasing a switch. A clock of around 1 – 2 Hz might work for a normal person. To show this, I add a frequency divider module to lower the clock on the board to approximately 1 Hz. (In a real application, it is more practical to generate such low frequency signal using, say, a 555 timer IC, instead of dividing a high frequency clock with long chains of FFs). This second video shows that, with proper switch pressing period, the FSM could perform the desired task. Error occurs sporadically whenever one pushes a switch for too long/short time. (Try holding a switch active. You’d see the LED toggles with same frequency as the clock)