An Introduction to Finite State Machine Design

A better design

As pointed out above, the flaw from our naive design is the incessant transitions between the on and off states during a switch press. To prevent such undesired behavior, an intermediate state is added between each pass to trap the state flow. The resulting state digram consists of 4 states like shown in figure 4. Suppose we start from S0 (LED off). When either swith is pressed, the state changes to S1, the LED turned on, and the state should stay at S1 as long as that switch remains pressed. After the switch is released, AB = 11 and the state shifts to S2 (LED still on). The LED-off state transitions through S2-S3-S4 bears similar explanation. To summarize, S1 and S3 are added to trap the state changes during each switch press event.

Figure 4: state diagram for new design of 3-way lighting

This new design sounds promising. So we go along with the implemenation. It is left as an exercise for the reader to derive state and output equations from state diagram in figure 4, using the same steps as in previous design — construct state-transition table, put in Karnaugh map, get a minimal state equation, and implement using DFFs and logic gates. Below we will take advantage of the software tool by using behavioral approach and HDL. First, the state diagram is redrawn as an ASM chart in figure 5. One could easily verify that it represents the same flow as state diagram in figure 4.

Figure 5: ASM chart for new design of 3-way lighting

It is quite straightforward to write an HDL module from the ASM.

Download an example in Verilog
sw3_asm4.v
Add the source to Xilnx ISE project. Synthesize. Translate. Fit. Program. Now it should be a good time to pop a beer…But, wait! from the testing in Video 3 below, it does have some tendency to work, but not so reliably. What goes wrong now?

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