Configure PIC24E to run at 70 MIPS

Configure the PLL

This is the essential part to make PIC fly. As shown in figure 2, there are 3 parameters that needs to be configured: PLLPRE, PLLDIV, and PLLPOST.

Figure 2: PLL block diagram (simplified from PIC24EP datasheet)

It also shows how the signals along the path are constrained. According to the datasheet, the relevant equations are

  • FCY = FOSC/2
  • FOSC = FIN x (M/(N1 x N2))
  • N1 = PLLPRE + 2
  • N2 = 2 x (PLLPOST + 1)
  • M = PLLDIV + 2

Let’s first consider the FRC case. The input clock frequency FIN = 7.37 MHz, and we want maximum output frequency FOSC = 140 MHz. There is some freedom in selecting 3 parameters to solve this problem. Our choice is to set PLLPRE = PLLPOST = 0, so N1 = N1 = 2. These values yields FPLLI = 3.685 MHz and FSYS = 280 MHz. From FSYS = FPLLI x M, we get M = 280/3.68 = 76. Hence PLLDIV = M – 2 = 76 – 2 = 74.

Now we just apply these 3 values to the chunk of code provided in Microchip document (which is executed after SW1 is pressed)

If (SW1)   {
       // Configure PLL prescaler, PLL postscaler, PLL divisor (FRC )
       PLLFBD = 74;   // M = 76
       CLKDIVbits.PLLPOST = 0;     // N2 = 2
       CLKDIVbits.PLLPRE=0;     // N1=2
       // initiate clock switch to FRC oscillator with PLL (NOSC=0b01)
       __builtin_write_OSCCONH(0x01);
       __builtin_write_OSCCONL(0x01);
       while (OSCCONbits.COSC != 0b001);
       while (OSCCONbits.LOCK != 1);
} while (SW1);

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