Audience may observe that I normally use general-purpose PCBs to build prototypes since the schematics are not too complicated to do so. They look unprofessional, but most could satisfy the desired functionality. Time and budget are also major factors for consideration. Nevertheless, once a design crystallized, it becomes burdensome to construct more than one prototype. This is a good point in time to consider creating a customized PCB.
Continue reading “Embedded Prototypes for Control Engineering”
In our previous article Configure PIC24 to run at 70 MIPS , I suggested a way to verify whether the PIC24E run at 70 MIPS by setting a timer output and measuring its period using an oscilloscope. If you are a normal person like me who does not have a scope sitting next to the computer, this approach might be infeasible (so why I proposed it in the first place? Doh!). Anyway, there is some other way that does not need a lab instrument. How about this? Let try setting up an asynchronous communication like UART. If the baud rate on the PIC24EP does not match that on the other side, say, our PC, then they couldn’t talk. To set up the baud rate, we have to put FCY = 70M into the equation. If the clock deviates from that value just a little bit, communcation would fail. Above all, we have a chance to learn how to set up UART communcation on the PIC24EP.
Continue reading “Verifying PIC24EP Clock Frequency by UART Module”
Since Microchip introduced their PIC24EP family of products, it took a while before they became available from major vendors in Thailand. This family (and its close relatives dsPIC33EP) is attractive for its 70 MIPS performance. It could not run at that speed right out of the package, considering a user’s choice of setup (such as oscillator type and frequency). So in this brief article, we show an example on how to configure PIC24EP to 70 MIPS. A PIC24EP256MC202 is used on our prototype, with 2 clock choices: the 7.37 MHz on-chip Internal Fast RC (FRC) oscillator, and an external 8 MHz crystal.
Continue reading “Configure PIC24E to run at 70 MIPS”
I2C (Inter-Integrated Circuit) is a serial communication protocol invented by Philips. The main advantage of using I2C is that it requires only 2 wires: clock and data, where several devices can be connected. In a typical arrangement, a processor acts as the bus master and devices as slaves, though multi-master setup is also possible.
Continue reading “PIC24E I2C communication with MCP4725”
A while ago on http://www.controlsystemslab.com (no longer maintained), we present an article on DC motor open-loop speed control , using a simple voltage command from ADC to drive the H-bridge driver. The PWM output is generated from output compare module of the dsPIC30F2010. That 16-bit digital signal processor is now quite dated. The reader would want to implement the scheme on a newer microcontroller.
At the time of this writing, PIC24EP (and dsPIC33E) series from Microchip is the latest product in the 16-bit range that could run at 70 MIPS performance. For those who want to port the code to PIC24EP, unfortunately, you have to modify the ADC and PWM routines. In this article we focus on the latter.
Continue reading “A Note on Output Compare (PWM) Module of PIC24E”
No matter how fast we advance in this digital era, the world is still analog in nature. In many industrial applications, an engineer needs to measure a continuous-time signal and store/process it digitally. For this reason, most microcontrollers have Analog-to-Digital Converter (ADC) modules as standard peripherals.
Continue reading “Simultaneous Sampling of 4 ADC Channels with PIC24E”
Roughly speaking, a synchronous Finite State Machine (FSM) refers to a digital circuit/system that has memory, and is driven by a clock signal to change from one state to another depending on the applied input and its previous state. This classification covers from the simplest circuit consisting of only one D flip-flop, to a high-performance computer system. One might refer to FSM as a sequential circuit, in contrast to a combinational circuit that is memoryless. With latest electronics/computer technology, an FSM of low to medium complexity can be designed and implemented rather easily using CPLD/FPGA and software tools. The main advantages of this approach are flexibility, compactness, and ease of maintenance. Hardwiring TTL/CMOS logic gate and DFF ICs together on a PCB is now considered outdated.
Previously on this website, we discussed some design and implementation of quadrature encoder interface circuits (see, for example, VHDL code for quadrature encoder receiver module and reference therein). That is an example of FSM which I normally use in my embedded system classes. I have found, however, that the circuit is somewhat too complicated to beginners who do not have enough background from a basic digital system course. So the purpose of this article is to provide a more simple example and hopefully help students grab the essence of two common approaches for FSM design: the State Diagram , and Algorithmic State Machine (ASM)
Continue reading “An Introduction to Finite State Machine Design”
Original document: Quadrature Encoder Receiver Module : An Implementation on FPGA (.pdf)
In the original document cited above, we discussed some designs of quadrature encoder receiver module where Verilog code listings were included. This supplementary article provides the same implementations using VHDL. The development flows remain the same for both design A and B, so we basically list the codes and show simulation results here without repeating the design details.
For Design A, the receiver module generates pulses at output pin U (up) or D (down), corresponding to whether A leads B, or A lags B, respectively (*). We showed the design process using STG (State Transition Graph) that yielded the results in equation (1) – (4) . The VHDL code for this implementation is in Listing 1 with simulation result shown in Figure 1. (The synthesis and behavioral simulation was performed using Xilinx Webpack 13.4 and Isim simulation, which could be downloaded from Xilinx website.
(*) It turns out that in the original document, the Karnaugh map for output U and D shuffles, so as the resulting equations (3) and (4). You could verify from the simulation in Figure 9. If this gives the wrong sense for your motor setup, simply switch equation (3) and (4). We do so in the VHDL code below.
Continue reading “VHDL code for quadrature encoder receiver module”